- Generated on Thu Jul 18 2013 11:53:00 for gr-baz Package by
1.7.6.1
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gr-baz Package
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00001 #ifndef _E4K_TUNER_H 00002 #define _E4K_TUNER_H 00003 00004 #include "rtl2832.h" 00005 00006 namespace RTL2832_NAMESPACE { namespace TUNERS_NAMESPACE { 00007 00008 class e4k; 00009 00010 } } // TUNERS_NAMESPACE // RTL2832_NAMESPACE 00011 00012 /////////////////////////////////////////////////////////////////////////////// 00013 00014 /* (C) 2011-2012 by Harald Welte <laforge@gnumonks.org> 00015 * 00016 * All Rights Reserved 00017 * 00018 * This program is free software; you can redistribute it and/or modify 00019 * it under the terms of the GNU General Public License as published by 00020 * the Free Software Foundation; either version 3 of the License, or 00021 * (at your option) any later version. 00022 * 00023 * This program is distributed in the hope that it will be useful, 00024 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00025 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00026 * GNU General Public License for more details. 00027 * 00028 * You should have received a copy of the GNU General Public License 00029 * along with this program. If not, see <http://www.gnu.org/licenses/>. 00030 */ 00031 00032 enum e4k_reg { 00033 E4K_REG_MASTER1 = 0x00, 00034 E4K_REG_MASTER2 = 0x01, 00035 E4K_REG_MASTER3 = 0x02, 00036 E4K_REG_MASTER4 = 0x03, 00037 E4K_REG_MASTER5 = 0x04, 00038 E4K_REG_CLK_INP = 0x05, 00039 E4K_REG_REF_CLK = 0x06, 00040 E4K_REG_SYNTH1 = 0x07, 00041 E4K_REG_SYNTH2 = 0x08, 00042 E4K_REG_SYNTH3 = 0x09, 00043 E4K_REG_SYNTH4 = 0x0a, 00044 E4K_REG_SYNTH5 = 0x0b, 00045 E4K_REG_SYNTH6 = 0x0c, 00046 E4K_REG_SYNTH7 = 0x0d, 00047 E4K_REG_SYNTH8 = 0x0e, 00048 E4K_REG_SYNTH9 = 0x0f, 00049 E4K_REG_FILT1 = 0x10, 00050 E4K_REG_FILT2 = 0x11, 00051 E4K_REG_FILT3 = 0x12, 00052 // gap 00053 E4K_REG_GAIN1 = 0x14, 00054 E4K_REG_GAIN2 = 0x15, 00055 E4K_REG_GAIN3 = 0x16, 00056 E4K_REG_GAIN4 = 0x17, 00057 // gap 00058 E4K_REG_AGC1 = 0x1a, 00059 E4K_REG_AGC2 = 0x1b, 00060 E4K_REG_AGC3 = 0x1c, 00061 E4K_REG_AGC4 = 0x1d, 00062 E4K_REG_AGC5 = 0x1e, 00063 E4K_REG_AGC6 = 0x1f, 00064 E4K_REG_AGC7 = 0x20, 00065 E4K_REG_AGC8 = 0x21, 00066 // gap 00067 E4K_REG_AGC11 = 0x24, 00068 E4K_REG_AGC12 = 0x25, 00069 // gap 00070 E4K_REG_DC1 = 0x29, 00071 E4K_REG_DC2 = 0x2a, 00072 E4K_REG_DC3 = 0x2b, 00073 E4K_REG_DC4 = 0x2c, 00074 E4K_REG_DC5 = 0x2d, 00075 E4K_REG_DC6 = 0x2e, 00076 E4K_REG_DC7 = 0x2f, 00077 E4K_REG_DC8 = 0x30, 00078 // gap 00079 E4K_REG_QLUT0 = 0x50, 00080 E4K_REG_QLUT1 = 0x51, 00081 E4K_REG_QLUT2 = 0x52, 00082 E4K_REG_QLUT3 = 0x53, 00083 // gap 00084 E4K_REG_ILUT0 = 0x60, 00085 E4K_REG_ILUT1 = 0x61, 00086 E4K_REG_ILUT2 = 0x62, 00087 E4K_REG_ILUT3 = 0x63, 00088 // gap 00089 E4K_REG_DCTIME1 = 0x70, 00090 E4K_REG_DCTIME2 = 0x71, 00091 E4K_REG_DCTIME3 = 0x72, 00092 E4K_REG_DCTIME4 = 0x73, 00093 E4K_REG_PWM1 = 0x74, 00094 E4K_REG_PWM2 = 0x75, 00095 E4K_REG_PWM3 = 0x76, 00096 E4K_REG_PWM4 = 0x77, 00097 E4K_REG_BIAS = 0x78, 00098 E4K_REG_CLKOUT_PWDN = 0x7a, 00099 E4K_REG_CHFILT_CALIB = 0x7b, 00100 E4K_REG_I2C_REG_ADDR = 0x7d, 00101 // FIXME 00102 }; 00103 00104 #define E4K_MASTER1_RESET (1 << 0) 00105 #define E4K_MASTER1_NORM_STBY (1 << 1) 00106 #define E4K_MASTER1_POR_DET (1 << 2) 00107 00108 #define E4K_SYNTH1_PLL_LOCK (1 << 0) 00109 #define E4K_SYNTH1_BAND_SHIF 1 00110 00111 #define E4K_SYNTH7_3PHASE_EN (1 << 3) 00112 00113 #define E4K_SYNTH8_VCOCAL_UPD (1 << 2) 00114 00115 #define E4K_FILT3_DISABLE (1 << 5) 00116 00117 #define E4K_AGC1_LIN_MODE (1 << 4) 00118 #define E4K_AGC1_LNA_UPDATE (1 << 5) 00119 #define E4K_AGC1_LNA_G_LOW (1 << 6) 00120 #define E4K_AGC1_LNA_G_HIGH (1 << 7) 00121 00122 #define E4K_AGC6_LNA_CAL_REQ (1 << 4) 00123 00124 #define E4K_AGC7_MIX_GAIN_AUTO (1 << 0) 00125 #define E4K_AGC7_GAIN_STEP_5dB (1 << 5) 00126 00127 #define E4K_AGC8_SENS_LIN_AUTO (1 << 0) 00128 00129 #define E4K_AGC11_LNA_GAIN_ENH (1 << 0) 00130 00131 #define E4K_DC1_CAL_REQ (1 << 0) 00132 00133 #define E4K_DC5_I_LUT_EN (1 << 0) 00134 #define E4K_DC5_Q_LUT_EN (1 << 1) 00135 #define E4K_DC5_RANGE_DET_EN (1 << 2) 00136 #define E4K_DC5_RANGE_EN (1 << 3) 00137 #define E4K_DC5_TIMEVAR_EN (1 << 4) 00138 00139 #define E4K_CLKOUT_DISABLE 0x96 00140 00141 #define E4K_CHFCALIB_CMD (1 << 0) 00142 00143 #define E4K_AGC1_MOD_MASK 0xF 00144 00145 enum e4k_agc_mode { 00146 E4K_AGC_MOD_SERIAL = 0x0, 00147 E4K_AGC_MOD_IF_PWM_LNA_SERIAL = 0x1, 00148 E4K_AGC_MOD_IF_PWM_LNA_AUTONL = 0x2, 00149 E4K_AGC_MOD_IF_PWM_LNA_SUPERV = 0x3, 00150 E4K_AGC_MOD_IF_SERIAL_LNA_PWM = 0x4, 00151 E4K_AGC_MOD_IF_PWM_LNA_PWM = 0x5, 00152 E4K_AGC_MOD_IF_DIG_LNA_SERIAL = 0x6, 00153 E4K_AGC_MOD_IF_DIG_LNA_AUTON = 0x7, 00154 E4K_AGC_MOD_IF_DIG_LNA_SUPERV = 0x8, 00155 E4K_AGC_MOD_IF_SERIAL_LNA_AUTON = 0x9, 00156 E4K_AGC_MOD_IF_SERIAL_LNA_SUPERV = 0xa, 00157 }; 00158 00159 enum e4k_band { 00160 E4K_BAND_VHF2 = 0, 00161 E4K_BAND_VHF3 = 1, 00162 E4K_BAND_UHF = 2, 00163 E4K_BAND_L = 3, 00164 }; 00165 00166 enum e4k_mixer_filter_bw { 00167 E4K_F_MIX_BW_27M = 0, 00168 E4K_F_MIX_BW_4M6 = 8, 00169 E4K_F_MIX_BW_4M2 = 9, 00170 E4K_F_MIX_BW_3M8 = 10, 00171 E4K_F_MIX_BW_3M4 = 11, 00172 E4K_F_MIX_BW_3M = 12, 00173 E4K_F_MIX_BW_2M7 = 13, 00174 E4K_F_MIX_BW_2M3 = 14, 00175 E4K_F_MIX_BW_1M9 = 15, 00176 }; 00177 00178 enum e4k_if_filter { 00179 E4K_IF_FILTER_MIX, 00180 E4K_IF_FILTER_CHAN, 00181 E4K_IF_FILTER_RC 00182 }; 00183 struct e4k_pll_params { 00184 uint32_t fosc; 00185 uint32_t intended_flo; 00186 uint32_t flo; 00187 uint16_t x; 00188 uint8_t z; 00189 uint8_t r; 00190 uint8_t r_idx; 00191 uint8_t threephase; 00192 }; 00193 00194 struct e4k_state { 00195 RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k* pTuner; 00196 uint8_t i2c_addr; 00197 enum e4k_band band; 00198 struct e4k_pll_params vco; 00199 }; 00200 00201 /////////////////////////////////////////////////////////////////////////////// 00202 00203 /* structure describing a field in a register */ 00204 struct reg_field { 00205 uint8_t reg; 00206 uint8_t shift; 00207 uint8_t width; 00208 }; 00209 00210 struct reg_field_ops { 00211 const struct reg_field *fields; 00212 const char **field_names; 00213 uint32_t num_fields; 00214 void *data; 00215 int (*write_cb)(void *data, uint32_t reg, uint32_t val); 00216 uint32_t (*read_cb)(void *data, uint32_t reg); 00217 }; 00218 00219 enum cmd_op { 00220 CMD_OP_GET = (1 << 0), 00221 CMD_OP_SET = (1 << 1), 00222 CMD_OP_EXEC = (1 << 2), 00223 }; 00224 00225 uint32_t reg_field_read(struct reg_field_ops *ops, struct reg_field *field); 00226 int reg_field_write(struct reg_field_ops *ops, struct reg_field *field, uint32_t val); 00227 int reg_field_cmd(struct cmd_state *cs, enum cmd_op op, 00228 const char *cmd, int argc, char **argv, 00229 struct reg_field_ops *ops); 00230 00231 /////////////////////////////////////////////////////////////////////////////// 00232 00233 int e4k_init(struct e4k_state *e4k, bool enable_dc_offset_loop = true, bool set_manual_gain = false); 00234 int e4k_if_gain_set(struct e4k_state *e4k, uint8_t stage, int8_t value); 00235 int e4k_mixer_gain_set(struct e4k_state *e4k, int8_t value); 00236 int e4k_commonmode_set(struct e4k_state *e4k, int8_t value); 00237 int e4k_tune_freq(struct e4k_state *e4k, uint32_t freq); 00238 int e4k_tune_params(struct e4k_state *e4k, struct e4k_pll_params *p); 00239 int e4k_compute_pll_params(struct e4k_pll_params *oscp, uint32_t fosc, uint32_t intended_flo); 00240 int e4k_if_filter_bw_get(struct e4k_state *e4k, enum e4k_if_filter filter); 00241 int e4k_if_filter_bw_set(struct e4k_state *e4k, enum e4k_if_filter filter, 00242 uint32_t bandwidth); 00243 int e4k_if_filter_chan_enable(struct e4k_state *e4k, int on); 00244 int e4k_rf_filter_set(struct e4k_state *e4k); 00245 /* 00246 int e4k_reg_write(struct e4k_state *e4k, uint8_t reg, uint8_t val); 00247 int e4k_reg_read(struct e4k_state *e4k, uint8_t reg); 00248 */ 00249 int sam3u_e4k_init(struct e4k_state *e4k, void *i2c, uint8_t slave_addr); 00250 void sam3u_e4k_power(struct e4k_state *e4k, int on); 00251 void sam3u_e4k_stby(struct e4k_state *e4k, int on); 00252 00253 00254 int e4k_manual_dc_offset(struct e4k_state *e4k, int8_t iofs, int8_t irange, int8_t qofs, int8_t qrange); 00255 int e4k_dc_offset_calibrate(struct e4k_state *e4k); 00256 int e4k_dc_offset_gen_table(struct e4k_state *e4k); 00257 00258 /////////////////////////////////////////////////////////////////////////////// 00259 00260 namespace RTL2832_NAMESPACE { namespace TUNERS_NAMESPACE { 00261 00262 class e4k : public RTL2832_NAMESPACE::tuner_skeleton 00263 { 00264 IMPLEMENT_INLINE_TUNER_FACTORY(e4k) 00265 public: 00266 e4k(demod* p); 00267 public: 00268 inline virtual const char* name() const 00269 { return "Elonics E4K"; } 00270 public: 00271 int initialise(tuner::PPARAMS params = NULL); 00272 int set_frequency(double freq); 00273 int set_bandwidth(double bw); 00274 int set_gain(double gain); 00275 int set_gain_mode(int mode); 00276 int set_auto_gain_mode(bool on = true); 00277 bool calc_appropriate_gain_mode(int& mode)/* const*/; 00278 private: 00279 int update_gain_mode(); 00280 public: 00281 struct e4k_state m_stateE4K; 00282 }; 00283 00284 } } // TUNERS_NAMESPACE, RTL2832_NAMESPACE 00285 00286 /////////////////////////////////////////////////////////////////////////////// 00287 00288 #define RTL2832_E4000_ADDITIONAL_INIT_REG_TABLE_LEN 34 00289 00290 #define RTL2832_E4000_LNA_GAIN_TABLE_LEN 16 00291 #define RTL2832_E4000_LNA_GAIN_ADD_TABLE_LEN 8 00292 #define RTL2832_E4000_MIXER_GAIN_TABLE_LEN 2 00293 #define RTL2832_E4000_IF_STAGE_1_GAIN_TABLE_LEN 2 00294 #define RTL2832_E4000_IF_STAGE_2_GAIN_TABLE_LEN 4 00295 #define RTL2832_E4000_IF_STAGE_3_GAIN_TABLE_LEN 4 00296 #define RTL2832_E4000_IF_STAGE_4_GAIN_TABLE_LEN 4 00297 #define RTL2832_E4000_IF_STAGE_5_GAIN_TABLE_LEN 8 00298 #define RTL2832_E4000_IF_STAGE_6_GAIN_TABLE_LEN 8 00299 00300 #define RTL2832_E4000_LNA_GAIN_BAND_NUM 2 00301 #define RTL2832_E4000_MIXER_GAIN_BAND_NUM 2 00302 00303 #define RTL2832_E4000_RF_BAND_BOUNDARY_HZ 300000000 00304 00305 #define RTL2832_E4000_LNA_GAIN_ADDR 0x14 00306 #define RTL2832_E4000_LNA_GAIN_MASK 0xf 00307 #define RTL2832_E4000_LNA_GAIN_SHIFT 0 00308 00309 #define RTL2832_E4000_LNA_GAIN_ADD_ADDR 0x24 00310 #define RTL2832_E4000_LNA_GAIN_ADD_MASK 0x7 00311 #define RTL2832_E4000_LNA_GAIN_ADD_SHIFT 0 00312 00313 #define RTL2832_E4000_MIXER_GAIN_ADDR 0x15 00314 #define RTL2832_E4000_MIXER_GAIN_MASK 0x1 00315 #define RTL2832_E4000_MIXER_GAIN_SHIFT 0 00316 00317 #define RTL2832_E4000_IF_STAGE_1_GAIN_ADDR 0x16 00318 #define RTL2832_E4000_IF_STAGE_1_GAIN_MASK 0x1 00319 #define RTL2832_E4000_IF_STAGE_1_GAIN_SHIFT 0 00320 00321 #define RTL2832_E4000_IF_STAGE_2_GAIN_ADDR 0x16 00322 #define RTL2832_E4000_IF_STAGE_2_GAIN_MASK 0x6 00323 #define RTL2832_E4000_IF_STAGE_2_GAIN_SHIFT 1 00324 00325 #define RTL2832_E4000_IF_STAGE_3_GAIN_ADDR 0x16 00326 #define RTL2832_E4000_IF_STAGE_3_GAIN_MASK 0x18 00327 #define RTL2832_E4000_IF_STAGE_3_GAIN_SHIFT 3 00328 00329 #define RTL2832_E4000_IF_STAGE_4_GAIN_ADDR 0x16 00330 #define RTL2832_E4000_IF_STAGE_4_GAIN_MASK 0x60 00331 #define RTL2832_E4000_IF_STAGE_4_GAIN_SHIFT 5 00332 00333 #define RTL2832_E4000_IF_STAGE_5_GAIN_ADDR 0x17 00334 #define RTL2832_E4000_IF_STAGE_5_GAIN_MASK 0x7 00335 #define RTL2832_E4000_IF_STAGE_5_GAIN_SHIFT 0 00336 00337 #define RTL2832_E4000_IF_STAGE_6_GAIN_ADDR 0x17 00338 #define RTL2832_E4000_IF_STAGE_6_GAIN_MASK 0x38 00339 #define RTL2832_E4000_IF_STAGE_6_GAIN_SHIFT 3 00340 00341 #define RTL2832_E4000_TUNER_OUTPUT_POWER_UNIT_0P1_DBM -100 00342 00343 #define RTL2832_E4000_TUNER_MODE_UPDATE_WAIT_TIME_MS 1000 00344 00345 #endif /* _E4K_TUNER_H */
1.7.6.1